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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. ad5304/ad5314/ad5324 * 2.5 v to 5.5 v, 500 a, quad voltage output 8-/10-/12-bit dacs in 10-lead msop * protected by u.s. patent no. 5,969,657; other patents pending. features ad5304: 4 buffered 8-bit dacs in 10-lead msop a version: 1 lsb inl, b version: 0.625 lsb inl ad5314: 4 buffered 10-bit dacs in 10-lead msop a version: 4 lsb inl, b version: 2.5 lsb inl ad5324: 4 buffered 12-bit dacs in 10-lead msop a version: 16 lsb inl, b version: 10 lsb inl low power operation: 500 a @ 3 v, 600 a @ 5 v 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 80 na @ 3 v, 200 na @ 5 v double-buffered input logic output range: 0 v to v ref power-on reset to 0 v simultaneous update of outputs ( ldac function) low power, spi , qspi, microwire, and dsp compatible 3-wire serial interface on-chip rail-to-rail output buffer ampli?rs temperature range ?0 c to +105 c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control functional block diagram input register v out a buffer dac register string dac a v dd refin gnd ad5304/ad5314/ad5324 input register v out b buffer dac register input register v out c buffer dac register input register v out d buffer dac register power-on reset sync sclk din interface logic power-down logic ldac string dac b string dac c string dac d general description the ad5304/ad5314/ad5324 are quad 8-, 10-, and 12-bit buffered voltage output dacs in a 10-lead msop that operate from a single 2.5 v to 5.5 v supply, consuming 500 m a at 3 v. their on-chip output ampli?rs allow rail-to-rail output swing to be achieved with a slew rate of 0.7 v/ m s. a 3-wire serial interface is used, which operates at clock rates up to 30 mhz and is compatible with standard spi, qspi, microwire, and dsp interface standards. the references for the four dacs are derived from one refe rence pin. the outputs of all dacs may be updated simultaneously using the software ldac function. the parts incorporate a power-on reset circuit, which ensures that the dac outputs power up to 0 v and remain there until a valid write takes place to the device. the parts contain a power-down feature that reduces the current consumption of the device to 200 na @ 5 v (80 na @ 3 v). the low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equip- ment. the power consumption is 3 mw at 5 v, 1.5 mw at 3 v, reducing to 1 m w in power-down mode.
rev. d e2e ad5304/ad5314/ad5324especifications (v dd = 2.5 v to 5.5 v; v ref = 2 v; r l = 2 k to gnd; c l = 200 pf to gnd; all specitcations t min to t max , unless otherwise noted.) a version 2 b version 2 parameter 1 min typ max min typ max unit conditions/comments dc performance 3, 4 ad5304 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5314 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5324 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 0.4 3% of fsr see figures 2 and 3 gain error 0.15 1 0.15 1% of fsr see figures 2 and 3 lower deadband 20 60 20 60 mv lower deadband exists only if offset error is negative. offset error drift 5 e12 e12 ppm of fsr/ v dd = 10% dc crosstalk 5 200 200 m vr l = 2 k w to gnd or v dd dac reference inputs 5 v ref input range 0.25 v dd 0.25 v dd v v ref input impedance 37 45 37 45 k w normal operation >10 >10 m w power-down mode reference feedthrough e90 e90 db frequency = 10 khz output characteristics 5 minimum output voltage 6 0.001 0.001 v this is a measure of the minimum and maximum maximum output voltage 6 v dd e 0.001 v dd e 0.001 v drive capability of the output ampliter. dc output impedance 0.5 0.5 w short circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 m s coming out of power-down mode. v dd = 5 v 55 m s coming out of power-down mode. v dd = 3 v logic inputs 5 input current 1 1 m a v il , input low voltage 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v v ih , input high voltage 2.4 2.4 v v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 7 v dd = 4.5 v to 5.5 v 600 900 600 900 m av ih = v dd and v il = gnd v dd = 2.5 v to 3.6 v 500 700 500 700 m av ih = v dd and v il = gnd i dd (power-down mode) v dd = 4.5 v to 5.5 v 0.2 1 .02 1 m av ih = v dd and v il = gnd v dd = 2.5 v to 3.6 v 0.08 1 0.08 1 m av ih = v dd and v il = gnd notes 1 see the terminology section. 2 temperature range (a, b version): e40
rev. d ad5304/ad5314/ad5324 e3e ac characteristics 1 a, b version 3 parameter 2 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5304 6 8 m s 1/4 scale to 3/4 scale change (0x40 to 0xc0) ad5314 7 9 m s 1/4 scale to 3/4 scale change (0x100 to 0x300) ad5324 8 10 m s 1/4 scale to 3/4 scale change (0x400 to 0xc00) slew rate 0.7 v/ m s major-code transition glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 1 nv-s digital crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p total harmonic distortion e70 db v ref = 2.5 v 0.1 v p-p. frequency = 10 khz notes 1 guaranteed by design and characterization, not production tested. 2 see the terminology section. 3 temperature range (a, b version): e40
rev. d e4e ad5304/ad5314/ad5324 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad5304/ad5314/ad5324 feature proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2 (t a = 25 ja ja thermal impedance . . . . . . . . . . . . . . . . . . . . . 206 jc thermal impedance . . . . . . . . . . . . . . . . . . . . . . 44
rev. d ad5304/ad5314/ad5324 e5e pin configuration top view (not to scale) 10 9 8 7 6 1 2 3 4 5 v dd v out a gnd din sclk sync v out d ad5304/ ad5314/ ad5324 v out b v out c refin pin function descriptions pin no. mnemonic function 1v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled to gnd. 2v out ab uffered analog output voltage from dac a. the output ampliter has rail-to-rail operation. 3v out bb uffered analog output voltage from dac b. the output ampliter has rail-to-rail operation. 4v out cb uffered analog output voltage from dac c. the output ampliter has rail-to-rail operation. 5 refin reference input pin for all four dacs. it has an input range from 0.25 v to v dd . 6v out db uffered analog output voltage from dac d. the output ampliter has rail-to-rail operation. 7g nd ground reference point for all circuitry on the part. 8d in serial data input. this device has a 16-bit shift register. data is clocked into the register on the falling edge of the serial clock input. the din input buffer is powered down after each write cycle. 9 sclk serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at clock speeds up to 30 mhz. the sclk input buffer is powered down after each write cycle. 10 sync active low control input. this is the frame synchronization signal for the input data. when sync goes low, it enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. if sync is taken high before the 16th falling edge of sclk, the rising edge of sync acts as an interrupt and the write sequence is ignored by the device.
rev. d ? ad5304/ad5314/ad5324 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer func tion. typical inl versus code plots can be seen in tpcs 1, 2, and 3. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a speci?d differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl versus code plots can be seen in tpcs 4, 5, and 6. offset error this is a measure of the offset error of the dac and the output ampli?r. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the devia- tion in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/ c. power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at m idscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being up dated. it is expressed in db. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally speci?d as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device when the dac output is not being written to ( sync held high). it is speci?d in nv-s and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac bit set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the ampli?rs within the dac have a ?ite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenu ated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics p resent on the dac output. it is measured in db. actual ideal gain error plus offset error output voltage negative offset error dac code amplifier footroom (1mv) negative offset error dead band codes figure 2. transfer function with negative offset output voltage positive offset dac code gain error plus offset error actual ideal figure 3. transfer function with positive offset
rev. d t ypical performance characteristicsead5304/ad5314/ad5324 e7e code inl error (lsb) 1.0 0.5 e1.0 050 250 100 150 200 0 e0.5 t a = 25 c v dd = 5v tpc 1. ad5304 typical inl plot code dnl error (lsb) 050 250 100 150 200 e0.1 e0.2 e0.3 0.3 0.1 0.2 0 t a = 25 c v dd = 5v tpc 4. ad5304 typical dnl plot v ref (v) error (lsb) 0.50 0.25 e0.50 01 5 234 0 e0.25 v dd = 5v t a = 25 c max inl max dnl min dnl min inl tpc 7. ad5304 inl and dnl error vs. v ref code inl error (lsb) 3 0 200 1000 400 600 800 0 e1 e2 e3 2 1 t a = 25 c v dd = 5v tpc 2. ad5314 typical inl plot code dnl error (lsb) 0.4 e0.4 600 400 800 1000 0 e0.6 0.6 0.2 e0.2 t a = 25 c v dd = 5v 200 0 tpc 5. ad5314 typical dnl plot temperature ( c) error (lsb) 0.5 0.2 e0.5 40 0 40 0 e0.2 v dd = 5v v ref = 3v max inl 80 120 e0.4 e0.3 e0.1 0.1 0.3 0.4 max dnl min inl min dnl tpc 8. ad5304 inl error and dnl error vs. temperature code inl error (lsb) 12 0 e4 e8 8 4 0 4000 1000 2000 3000 e12 t a = 25 c v dd = 5v tpc 3. ad5324 typical inl plot code dnl error (lsb) 0.5 2000 3000 4000 0 e1.0 1.0 e0.5 t a = 25 c v dd = 5v 1000 0 tpc 6. ad5324 typical dnl plot gain error temperature ( c) error (%) 1.0 0.5 e1.0 40 0 40 0 e0.5 v dd = 5v v ref = 2v offset error 80 120 tpc 9. ad5304 offset error and gain error vs. temperature
rev. d e8e ad5304/ad5314/ad5324 gain error v dd (v) error (%) 0.2 e0.6 01 3 0 e0.4 t a = 25 c v ref = 2v 46 e0.5 e0.3 e0.2 e0.1 0.1 25 offset error tpc 10. offset error and gain error vs. v dd v dd (v) i dd ( a) 600 0 500 100 200 300 400 2.5 3.0 4.0 4.5 5.5 3.5 5.0 +105 c 40 c +25 c tpc 13. supply current vs. supply voltage v out a 5s ch1 ch2 sclk t a = 25 c v dd = 5v v ref = 5v ch1 1v, ch2 5v, time base= 1 s/div tpc 16. half-scale settling (1/4 to 3/4 scale code change) 5v source sink/source current (ma) v out (v) 5 0 01 3 4 46 1 2 3 25 3v source 3v sink 5v sink tpc 11. v out source and sink current capability v dd (v) i dd ( a) 0.5 0 0.4 0.1 0.2 0.3 2.5 3.0 4.0 4.5 5.5 3.5 5.0 105 c 40 c 25 c tpc 14. power-down current vs. supply voltage v dd ch1 ch2 v out a t a = 25 c v dd = 5v v ref = 2v ch1 2v, ch2 200mv, time base = 200 s/div tpc 17. power-on reset to 0 v code i dd ( a) 600 0 500 100 200 300 400 t a = 25 c v dd = 5v v ref = 2v zero scale full scale tpc 12. supply current vs. dac code v logic (v) 1000 400 0 0.5 4.5 1.5 2.5 3.5 700 600 900 800 i dd ( a) 1.0 2.0 3.0 4.0 5.0 500 t a = 25 c v dd = 5v v dd = 3v tpc 15. supply current vs. logic input voltage t a = 25 c v dd = 5v v ref = 2v v out a ch1 ch2 sclk ch1 500mv, ch2 5v, time base= 1 s/div tpc 18. exiting power-down to midscale
rev. d ad5304/ad5314/ad5324 e9e i dd ( a) frequency 300 350 600 400 450 500 550 v dd = 5v v dd = 3v tpc 19. i dd histogram with v dd = 3 v and v dd = 5 v v dd = 5v t a = 25 c v ref (v) full-scale error (v) 0.02 e0.02 01 3 0.01 e0.01 46 0 25 tpc 22. full-scale error vs. v ref 1 s /div 2.48 2.49 v out (v) 2.47 2.50 tpc 20. ad5324 major-code transition glitch energy 150ns/div 1mv/div tpc 23. dac-to-dac crosstalk frequency (hz) 10 e40 10 e20 e30 0 e10 db 100 1k 10k 100k 1m 10m e50 e60 tpc 21. multiplying bandwidth (small-signal frequency response)
rev. d e10e ad5304/ad5314/ad5324 functional description the ad5304/ad5314/ad5324 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each contains four output buffer ampliters and is written to via a 3-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer ampliters provide rail-to-rail output swing with a slew rate of 0.7 v/ m s. the four dacs share a single reference input pin. the devices have programmable power-down modes, in which all dacs may be turned off completely with a high impedance output. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer ampliter. the voltage at the refin pin provides the reference voltage for the dac. figure 4 shows a block diagram of the dac architecture. since the input coding to the dac is straight binary, the ideal output voltage is given by v vd out ref n = 2 where d = decimal equivalent of the binary code, which is loaded to the dac register: 0e255 for ad5304 (8 bits) 0e1023 for ad5314 (10 bits) 0e4095 for ad5324 (12 bits) n = dac resolution input register refin output buffer amplifier v out a resistor string dac register figure 4. dac channel architecture resistor string the resistor string section is shown in figure 5. it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output ampliter. the voltage is tapped off by closing one of the switches connecting the string to the ampliter. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier figure 5. resistor string dac reference inputs there is a single reference input pin for the four dacs. the reference input is unbuffered. the user can have a reference voltage as low as 0.25 v and as high as v dd since there is no restriction due to headroom and footroom of any reference ampliter. it is recommended to use a buffered reference in the external circuit (e.g., ref192). the input impedance is typically 45 k w . output ampliter the output buffer ampliter is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 v to v dd when the reference is v dd . it is capable of driving a load of 2 k w to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output ampliter can be seen in the plot in tpc 11. the slew rate is 0.7 v/ m s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 m s. power-on reset the ad5304/ad5314/ad5324 are provided with a power-on reset function, so that they power up in a detned state. the power-on state is
rev. d ad5304/ad5314/ad5324 e11e address and control bits pd 0: all four dacs go into power-down mode, consuming only 200 na @ 5 v. the dac outputs enter a high impedance state. 1: normal operation. ldac 0: all four dac registers and, therefore, all dac outputs updated simultaneously on completion of the write sequence. 1: only addressed input register is updated. t here is no change in the content of the dac registers. the ad5324 uses all 12 bits of dac data; the ad5314 uses 10 bits and ignores the 2 lsb. the ad5304 uses eight bits and ignores the last four bits. the data format is straight binary, with all 0s corresponding to 0 v output and all 1s corresponding to full-scale output (v ref e 1 lsb). the sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. data can be trans ferred into the device only while sync is low. to start the serial data transfer, sync should be taken low, observing the mini- mum sync to sclk falling edge setup time, t 4 . after sync goes low, serial data will be shifted into the device?s input shift register on the falling edges of sclk for 16 clock pulses. any data and clock pulses after the 16th falling edge of sclk will be ignored because the sclk and din input buffers are powered down. no further serial data transfer will occur until sync is taken high and low again. sync may be taken high after the falling edge of the 16th sclk pulse, observing the minimum sclk falling edge to sync rising edge time, t 7 . after the end of serial data transfer, data will automatically be transferred from the input shift register to the input register of the selected dac. if sync is taken high before the 16th falling edge of sclk, the data transfer will be aborted and the dac input registers will not be updated. when data has been transferred into three of the dac input registers, all dac registers and all dac outputs may simul- taneously be updated by setting ldac low when writing to the rem aining dac input register. low power serial interface to reduce the power consumption of the device even further, the interface powers up fully only when the device is being writ- ten to, i.e., on the falling edge of sync . as soon as the 16-bit control word has been written to the part, the sclk and din input buffers are powered down. they power up again only following a falling edge of sync . double-buffered interface the ad5304/ad5314/ad5324 dacs have double-buffered interfaces consisting of two banks of registers?input registers and dac registers. the input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac regis ter contains the digital code used by the resistor string. access to the dac register is controlled by the ldac bit. when the ldac bit is set high, the dac register is latched and hence the input register may change state without affecting the con tents of the dac register. however, when the ldac bit is set low, all dac registers are updated after a complete write sequence. this is useful if the user requires simultaneous updating of all dac outputs. the user may write to three of the input registers individually and then, by setting the ldac bit low when writ- ing to the remaining dac input register, all outputs will update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are tlled with the contents of the input registers. in the case of the ad5304/ad5314/ ad5324, the part will update the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down mode the ad5304/ad5314/ad5324 have low power consumption, dissipating only 1.5 mw with a 3 v supply and 3 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into power-down mode, which is selected by a 0 on bit 13 ( pd ) of the control word. a0 ldac pd d7 d6 d5 d4 d3 d2 d1 bit0 (lsb) a1 d0 0 0 x bit15 (msb) data bits x figure 6. ad5304 input shift register contents a0 ldac pd d9 d8 d7 d6 d5 d4 d3 bit0 (lsb) a1 d2 xx bit15 (msb) data bits d1 d0 figure 7. ad5314 input shift register contents a0 ldac pd d11 d10 d9 d8 d7 d6 d5 bit0 (lsb) a1 d4 bit15 (msb) data bits d3 d2 d1 d0 figure 8. ad5324 input shift register contents
rev. d e12e ad5304/ad5314/ad5324 when the pd bit is set to 1, all dacs work normally with a typical power consumption of 600 m a at 5 v (500 m a at 3 v). however, in power-down mode, the supply current falls to 200 na at 5 v (80 na at 3 v) when all dacs are powered down. not only does the supply current drop, but the output stage is also internally switched from the output of the ampliter, making it open-circuit. this has the advantage that the output is three- stated while the part is in power-down mode, and provides a detned input condition for whatever is connected to the output of the dac ampliter. the output stage is illustrated in figure 9. the bias generator, the output ampliter, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the registers are unaffected when in power-down. the time to exit power-down is typically 2.5 m s for v dd = 5 v and 5 m s when v dd = 3 v. this is the time from the falling edge of the 16th sclk pulse to when the output voltage deviates from its power- down voltage. see tpc 18 for a plot. amplifier power-down circuitry resistor string dac v out figure 9. output stage during power-down microprocessor interfacing ad5304/ad5314/ad5324 to adsp-2101/adsp-2103 interface figure 10 shows a serial interface between the ad5304/ad 5314/ ad5324 and the adsp-2101/adsp-2103. the adsp-2101/ adsp-2103 should be set up to operate in the sport transmit alternate framing mode. the adsp-2101/adsp-2103 sport is programmed through the sport control register and should be contgured as follows: internal clock operation, active-low fram- ing, 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is clocked out on each rising edge of the dsp?s serial clock and clocked into the ad5304/ad5314/ad5324 on the falling edge of the dac?s sclk. ad5304/ ad5314/ ad5324 * sclk din sync tfs dt sclk adsp-2101/ adsp-2103 * * additional pins omitted for clarity. figure 10. ad5304/ad5314/ad5324 to adsp-2101/ adsp-2103 interface ad5304/ad5314/ad5324 to 68hc11/68l11 interface figure 11 shows a serial interface between the ad5304/ad 5314/ ad5324 and the 68hc11/68l11 microcontroller. sck of the 68hc11/68l11 drives the sclk of the ad5304/ad5314/ ad5324, while the mosi output drives the serial data line (din) of the dac. the sync signal is derived from a port line (pc7). the setup conditions for correct operation of this interface are as follows: the 68hc11/68l11 should be contgured so that its cpol bit is a 0 and its cpha bit is a 1. when data is being transmitted to the dac, the sync line is taken low (pc7). when the 68hc11/68l11 is contgured as above, data appearing on the mosi output is valid on the falling edge of sck. serial data from the 68hc11/68l11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. data is transmitted msb trst. to load data to the ad5304/ad5314/ ad5324, pc7 is left low after the trst eight bits are transferred, a second serial write operation is per formed to the dac, and pc7 is taken high at the end of this procedure. din sclk sync pc7 sck mosi 68hc11/68l11 * * additional pins omitted for clarity. ad5304/ ad5314/ ad5324 * figure 11. ad5304/ad5314/ad5324 to 68hc11/ 68l11 interface ad5304/ad5314/ad5324 to 80c51/80l51 interface figure 12 shows a serial interface between the ad5304/ad 5314/ ad5324 and the 80c51/80l51 microcontroller. the setup for the interface is as follows: txd of the 80c51/80l51 drives sclk of the ad5304/ad5314/ad5324, while rxd drives the serial data line of the part. the sync signal is again derived from a bit-programmable pin on the port. in this case, port line p3.3 is used. when data is to be transmitted to the ad5304/ ad5314/ad5324, p3.3 is taken low. the 80c51/80l51 trans- mits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. to load data to the dac, p3.3 is left low after the trst eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. p3.3 is taken high following the completion of this cycle. the 80c51/ 80l51 outputs the serial data in a format that has the lsb trst. the ad5304/ad5314/ad5324 requires its data with the msb as the trst bit received. the 80c51/80l51 transmit routine should take this into account. din sclk sync p3.3 txd rxd 80c51/80l51 * * additional pins omitted for clarity. ad5304/ ad5314/ ad5324 * figure 12. ad5304/ad5314/ad5324 to 80c51/ 80l51 interface
rev. d ad5304/ad5314/ad5324 e13e ad5304/ad5314/ad5324 to microwire interface figure 13 shows an interface between the ad5304/ad5314/ ad5324 and any microwire compatible device. serial data is shifted out on the falling edge of the serial clock, sk, and is clocked into the ad5304/ad5314/ad5324 on the rising edge of sk , which corresponds to the falling edge of the dac?s s clk. din sclk sync cs sk so microwire * * additional pins omitted for clarity. ad5304/ ad5314/ ad5324 * figure 13. ad5304/ad5314/ad5324 to microwire interface applications typical application circuit the ad5304/ad5314/ad5324 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 v to v dd . m ore typically, these devices are used with a txed, precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference would be the ad589, a 1.23 v band gap refer- ence. figure 14 shows a typical setup for the ad5304/ad5314/ ad5324 when using an external reference. ad5304/ ad5314/ ad5324 v out b v out d gnd sclk sync serial interface v out ext ref 0.1 f v out a v out c refin ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v v dd = 2.5v to 5.5v v in a0 10 f 1 f din figure 14. ad5304/ad5314/ad5324 using external reference if an output range of 0 v to v dd is required, the simplest solu- tion is to connect the reference input to v dd . as this supply may not be very accurate and may be noisy, the ad5304/ad5314/ ad5324 may be powered from the reference voltage; for exam ple, using a 5 v reference such as the ref195. the ref195 will output a steady supply voltage for the ad5304/ad5314/ad 5324. the current required from the ref195 is 600 m a supply cur- rent and approximately 112 m a into the reference input. this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k w load on each output) is 712 4 5 10 2 70 m avk ma + () = /. w the load regulation of the ref195 is typically 2 ppm/ma, w hich results in an error of 5.4 ppm (27 m v) for the 2.7 ma current drawn from it. this corresponds to a 0.0014 lsb error at eight bits and 0.022 lsb error at 12 bits. bipolar operation using the ad5304/ad5314/ad5324 the ad5304/ad5314/ad5324 have been designed for single- supply operation, but a bipolar output range is also possible using the circuit in figure 15. this circuit will give an output voltage range of 5 v. rail-to-rail operation at the ampliter output is achievable using an ad820 or an op295 as the output ampliter. +5v e5v ad820/ op295 10 f 6v to 16v ad5304 0.1 f v dd v out a r1 = 10k 5v r2 = 10k refin gnd v out v in ref195 1 f 5v sync din serial interface v out c v out d v out b gnd sclk figure 15. bipolar operation with the ad5304 the output voltage for any input code can be calculated as follows: v refin d r r r refin r r out n = () + () () ? ? ? ? ? 212 121 ? where d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with refin = 5 v, r 1 = r 2 = 10 k w : vdv out n = () 10 2 5 /e opto-isolated interface for process control applications the ad5304/ad5314/ad5324 have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. due to noise, safety requirements, or distance, it may be necessary to isolate the ad5304/ad5314/ad5324 from the controller. this can easily be achieved by using opto-isolators, which will provide isolation in excess of 3 kv. the actual data rate achieved may be limited by the type of optocouplers chosen. the serial loading structure of the ad5304/ad5314/ad5324 makes them ideally suited for use in opto-isolated applications. figure 16 shows an opto- isolated interface to the ad5304 where din, sclk, and sync are driven from optocouplers. the power supply to the part also needs to be isolated. this is done by using a transformer. on the dac side of the transformer, a 5 v regulator provides the 5 v supply required for the ad5304.
rev. d e14e ad5304/ad5314/ad5324 v dd sclk 10k ad5304 din sync v dd gnd v out a 0.1 f 10 f refin v out b sclk 5v regulator power v dd sync 10k v dd din 10k v out c v out d figure 16. ad5304 in an opto-isolated interface decoding multiple ad5304/ad5314/ad5324s the sync pin on the ad5304/ad5314/ad5324 can be used in applications to decode a number of dacs. in this applica- tion, all the dacs in the system receive the same serial clock and serial data, but the sync to only one of the devices will be active at any one time, allowing access to four channels in this 16-channel system. the 74hc139 is used as a 2-to-4-line de coder to address any of the dacs in the system. to prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. figure 17 shows a diagram of a typical setup for decoding multiple ad 5304 devices in a system. 74hc139 v cc v dd enable coded address 1g 1a 1b dgnd sync din sclk 1y0 1y1 1y2 1y3 sync din sclk sync din sclk sync din sclk sclk din ad5304 ad5304 ad5304 ad5304 v out a v out b v out c v out d v out a v out b v out c v out d v out a v out b v out c v out d v out a v out b v out c v out d figure 17. decoding multiple ad5304 devices in a system ad5304/ad5314/ad5324 as a digitally programmable wi n dow detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5304/ad5314/ad5324 is shown in figure 18. the upper and lower limits for the test are loaded to dacs a and b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led will indicate the fail condition. similarly, dacs c and d can be used for window detection on a second v in signal. sync 1/2 ad5304/ ad5314/ ad5324 * v dd 5v v out a gnd refin v in pass/ fail 1/2 cmp04 1/6 74hc05 fail pass 1k 0.1 f 10 f sclk din sclk din 1k v out b v ref * additional pins omitted for clarity sync figure 18. window detection power supply bypassing and grounding in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5304/ad5314/ad5324 is mounted should be designed so that the analog and digital sections are separated and contned to certain areas of the board. if the ad5304/ad5314/ad5324 is in a system where multiple devices require an agnd-to- dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5304/ad5314/ad5324 should have ample supply bypassing of 10 m f in parallel with 0.1 m f on the supply located as close to the package as possible, ideally right up against the device. the 10 m f capacitors are the tantalum bead type. the 0.1 m f capacitor should have low effective series resistance (esr) and effective series inductance (esi), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. the power supply lines of the ad5304/ad5314/ad5324 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip tech nique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
rev. d ad5304/ad5314/ad5324 e15e table ii. overview of ad53xx serial devices no. of settling part no. resolution dacs dnl interface time ( s) package pins singles ad5300 8 1 0.25 spi 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 visit www.analog.com/support/standard_linear/selection_guides/ad53xx.html for more information. table iii. overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time ( s) additional pin functions package pins singles buf gain hben clr ?? ? ?? ?? ? ?? ? ? ? ?? ? ?? ? ?? ?? ?? ??
rev. d c00929?8/03(d) ?6 ad5304/ad5314/ad5324 outline dimensions 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc 3.00 bsc 3.00 bsc 4.90 bsc pin 1 coplanarity 0.10 compliant to jedec standards mo-187ba revision history location page 8/03?ata sheet changed from rev. c to rev. d. added a version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . universal changes to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 added octals section to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

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